1. Field of the Invention
The present invention relates to a squarer, and more particularly to an extendable squarer.
2. Description of the Related Art
Square operations have been widely applied in VLSI circuits, communication systems and radar systems. Earlier, multipliers have been applied to execute the square operations. Due to the complicated operating systems or integrated circuits, hundreds of thousands of multipliers are required. This would cause the increase of costs.
In order to resolve the problem, square operation technology and circuits have been developed. FIG. 1 is a table of Booth multiplication. Referring to FIG. 1, y represents a multiplicand, x represents a multiplier and i represents the number of bits and an integer. Booth method checks three bits and skips two bits for each operation. Therefore, one bit will be overlapped and m/2 column of the partial product terms are generated as shown in FIG. 1.
FIG. 2 is a partial multiplication matrix of a prior art squarer. Referring to FIG. 2, A represents bit codes, and subscripts represent the bits of the bit codes. In FIG. 2, it shows a partial multiplication matrix of a 4-bit data (A0 A1 A2 A3) square operation.
In addition, the Booth encoding method is also applied for square operations. For example, before the Booth encoding method performs square operations for 8-bit data, the 8-bit data are shown as below:−b727+b626+ . . . +b020=B326+B224+B122+B020                 wherein b represents the bit codes of the 8-bit data, and the subscripts represent the bits of the bit codes. B1, B2, B3 and B4 represent the operators according to the Booth encoding method and are shown as below:Bi=−2b2i+1+b2i+b2i−1         
FIG. 3 is a partially folded multiplication matrix according to a 8-bit Booth method. Referring to FIG. 3, the square value of the 8-bit data can be shown as below:
            (                        2          ⁢                      B            3                    ⁢                      2            6                          +                  2          ⁢                      B            2                    ⁢                      2            4                          +                  2          ⁢                      B            1                    ⁢                      2            2                              )        ×          B      0        ⁢          2      0        +            B      0        ×          2      0        +            (                        2          ⁢                      B            3                    ⁢                      2            4                          +                  2          ⁢                      B            2                    ⁢                      2            2                              )        ×          B      1        ⁢          2      4        +            B      1        ×          B      1        ⁢          2      4        +            (              2        ⁢                  B          3                ⁢                  2          2                    )        ×          B      2        ⁢          2      8        +            B      2        ×          B      2        ⁢          2      8        +            B      3        ×          B      3        ⁢          2      12                      This formula can be simplified as below:(P023+C0)+(P123+C1)24+(P223+C2)28+C3212         wherein P and C are represented by the following formulas:Ci=Bi×Bi i=1, . . . , 4Pi=(−b725−2i+b624−2i+ . . . +b2+220+b2i+120)×Bi i=0, . . . , 2        
These prior art methods require a great size of the circuit. This requirement conflicts with the trend of integration of circuits.